Introducing Timepix2, a frame-based pixel detector readout ASIC measuring energy deposition and arrival time

The Timepix2 ASIC (application-specific integrated circuit) is the upgraded successor to the Timepix [1] hybrid pixel detector readout chip. Like the original, Timepix2 contains a matrix of 65k square pixels of 55 μm pitch that can be coupled to a similarly segmented semiconductor sensor, or integrated in an ionising gas detector. The pixels are programmable, with several operation modes and selectable counter depths (up to 18 bits for time-of-arrival, ToA, and up to 14 bits for time-over-threshold, ToT). In ToT and ToA mode, each pixel records the arrival time and energy deposited by particles interacting with the corresponding sensor segment, with an optional separation of timing resolution for ToT and ToA: down to 10 ns each. The gain of the frontend circuit can be programmed to adapt to the quantity of energy deposited in the sensor, yielding a large dynamic range of 0.38 ke− to 950 ke−. The frontend noise in adaptive gain mode is 380 e− rms. The design also introduces some power optimisation features to the Timepix portfolio, such as power masking on selectable parts of the pixel matrix. With all pixels powered on, using 100 MHz for both ToT and ToA clock frequencies, and assuming a sparse particle interaction with the pixels, the matrix is estimated to consume less than 900 mW based on simulation.

An introduction to the Medipix family ASICs

The first Medipix chip which aimed at permitting single photon counting on a sizable matrix of pixels was developed in the mid-1990’s. In the following 20 years two families of chips have evolved from that initial effort. The Medipix photon counting family of chips comprises Medipix, Medipix2 and Medipix3. A 4th generation chip, Medipix4, is under development. The Timepix chips were initially more aimed at single particle detection and that family comprises Timepix, the most recent Timepix2 chip (introduced in this Special Issue) and Timepix3. The 4th generation Timepix4 is also under development and a first version will be produced in 2019. This paper seeks to provide a brief introduction to the various members of the Medipix family and provide references to more detailed descriptions already available in the literature.

Medipix3: A 64 k pixel detector readout chip working in single photon counting mode with improved spectrometric performance

Medipix3 is a 256×256 channel hybrid pixel detector readout chip working in a single photon counting mode with a new inter-pixel architecture, which aims to improve the energy resolution in pixelated detectors by mitigating the effects of charge sharing between channels. Charges are summed in all 2×2 pixel clusters on the chip and a given hit is allocated locally to the pixel summing circuit with the biggest total charge on an event-by-event basis. Each pixel contains also two 12-bit binary counters with programmable depth and overflow control. The chip is configurable such that either the dimensions of each detector pixel match those of one readout pixel or detector pixels are four times greater in area than the readout pixels. In the latter case, event-by-event summing is still possible between the larger pixels. Each pixel has around 1600 transistors and the analog static power consumption is below 15 μW in the charge summing mode and 9 μW in the single pixel mode. The chip has been built in an 8-metal 0.13 μm CMOS technology. This paper describes the chip from the pixel to the periphery and first electrical results are summarized.

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