Publications

The first Medipix chip which aimed at permitting single photon counting on a sizable matrix of pixels was developed in the mid-1990’s. In the following 20 years two families of chips have evolved from that initial effort. The Medipix photon counting family of chips comprises Medipix, Medipix2 and Medipix3. A 4th generation chip, Medipix4, is under development. The Timepix chips were initially more aimed at single particle detection and that family comprises Timepix, the most recent Timepix2 chip (introduced in this Special Issue) and Timepix3. The 4th generation Timepix4 is also under development and a first version will be produced in 2019. This paper seeks to provide a brief introduction to the various members of the Medipix family and provide references to more detailed descriptions already available in the literature.

Medipix3 is a 256×256 channel hybrid pixel detector readout chip working in a single photon counting mode with a new inter-pixel architecture, which aims to improve the energy resolution in pixelated detectors by mitigating the effects of charge sharing between channels. Charges are summed in all 2×2 pixel clusters on the chip and a given hit is allocated locally to the pixel summing circuit with the biggest total charge on an event-by-event basis. Each pixel contains also two 12-bit binary counters with programmable depth and overflow control. The chip is configurable such that either the dimensions of each detector pixel match those of one readout pixel or detector pixels are four times greater in area than the readout pixels. In the latter case, event-by-event summing is still possible between the larger pixels. Each pixel has around 1600 transistors and the analog static power consumption is below 15 μW in the charge summing mode and 9 μW in the single pixel mode. The chip has been built in an 8-metal 0.13 μm CMOS technology. This paper describes the chip from the pixel to the periphery and first electrical results are summarized.